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as2842/3/4/5 current mode controller description the as2842 family of control ics provide pin-for-pin replace- ment of the industry standard uc3842 series of devices. the devices are redesigned to provide significantly improved tolerances in power supply manufacturing. the 2.5 v refer- ence has been trimmed to 1.0% tolerance. the oscillator discharge current is trimmed to provide guaranteed duty cycle clamping rather than specified discharge current. the circuit is more completely specified to guarantee all param- eters impacting power supply manufacturing tolerances. in addition, the oscillator and flip-flop sections have been enhanced to provide additional performance. the r t /c t pin now doubles as a synchronization input that can be easily driven from open collector/open drain logic outputs. this sync input is a high impedance input and can easily be used for externally clocked systems. the new flip-flop topology allows the duty cycle on the as2844/5 to be guaranteed between 49 and 50%. the as2843/5 requires less than 0.5 ma of start-up current over the full temperature range. pin configuration top view features ? 2.5 v bandgap reference trimmed to 1.0% and temperature-compensated ? extended temperature range from - 40 to 105 c ? as2842/3 oscillations trimmed for precision duty cycle clamp ? as2844/5 have exact 50% max duty cycle clamp ? advanced oscillator design simplifies synchronization ? improved specs on uvlo and hysteresis provide more predictable start-up and shutdown ? improved 5 v regulator provides better ac noise immunity ? guaranteed performance with current sense pulled below ground ? over-temperature shutdown 8l soic (d) 8 1 comp v reg 7 2 v fb v cc 6 3 i sense out 5 4 r t /c t gnd pdip (n) 8 1 comp v reg 7 2 v fb v cc 6 3 i sense out 5 4 r t /c t gnd ordering information description temperature range order codes 8-pin plastic dip -40 to 105 c as2842/3/4/5n 8-pin plastic soic -40 to 105 c as2842/3/4/5d-8 astec semiconductor 37
as2842/3/4/5 current mode controller astec semiconductor 38 functional block diagram pin function description pin number function description 1 comp this pin is the error amplifier output. typically used to provide loop compensation to maintain v fb at 2.5 v. 2v fb inverting input of the error amplifier. the non-inverting input is a trimmed 2.5 v bandgap reference. 3i sense a voltage proportional to inductor current is connected to the input. the pwm uses this information to terminate the gate drive of the output. 4r t /c t oscillator frequency and maximum output duty cycle are set by connecting a resistor (r t ) to v reg and a capacitor (c t ) to ground. pulling this pin to ground or to v reg will accomplish a synchronization function. 5 gnd circuit common ground, power ground, and ic substrate. 6 out this output is designed to directly drive a power mosfet switch. this output can sink or source peak currents up to 1a. the output for the as2844/5 switches at one-half the oscillator frequency. 7v cc positive supply voltage for the ic. 8v reg this 5 v regulated output provides charging current for the capacitor c t through the resistor r t . figure 1. block diagram of the as2842/3/4/5 + + + + 6 out 2 error amp 1 4 5 7 8 gnd v cc v reg r t /c t v fb comp s r ff s r ff (5.0 v) (2.5 v) (1.0 v) 2r r (5 v) (3.0 v) (1.3 v) (0.6 v) oscillator pwm comparator over temperature t ff clk ?2 [3844/45] clk [3842/43] 5 v regulator (5.0 v) ref ok (4 v) uvlo (4 v) pwm logic 3 + i sense
astec semiconductor current mode controller as2842/3/4/5 39 absolute maximum ratings parameter symbol rating unit supply voltage (i cc < 30 ma) v cc self-limiting v supply voltage (low impedance source) v cc 30 v output current i out 1a output energy (capacitive load) 5 m j analog inputs (pin 2, pin 3) C 0.3 to 30 v error amp sink current 10 ma maximum power dissipation p d 8l soic 750 mw 8l pdip 1000 mw maximum junction temperature t j 150 c storage temperature range t stg C 65 to 150 c lead temperature, soldering 10 seconds t l 300 c stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended conditions parameter symbol rating unit supply voltage v cc as2842,4 15 v as2843,5 10 v oscillator f osc 50 to 500 khz typical thermal resistances package q ja q jc typical derating 8l pdip 95 c/w 50 c/w 10.5 mw/ c 8l soic 175 c/w 45 c/w 5.7 mw/ c
as2842/3/4/5 current mode controller astec semiconductor 40 electrical characteristics electrical characteristics are guaranteed over full junction temperature range (-40 to 105 c ). ambient temperature must be derated based on power dissipation and package thermal characteristics. the conditions are: v cc = 15 v, r t = 10 k w, and c t = 3.3 nf, unless otherwise stated. to override uvlo, v cc should be raised above 17 v prior to test. parameter symbol test condition min typ max unit 5 v regulator output voltage v reg t j = 25 c, i reg = 1 ma 4.95 5.00 5.05 v line regulation psrr 12 v cc 25 v 2 10 mv load regulation 1 i reg 20 ma 2 10 mv temperature stability 1 tc reg 0.2 0.4 mv/ c total output variation 1 line, load, temperature 4.85 5.15 v long-term stability 1 over 1,000 hrs at 25 c525mv output noise voltage v noise 10 hz f 100 khz, t j = 25 c50 m v short circuit current i sc 30 100 180 ma 2.5 v internal reference nominal voltage v fb t = 25 c; i reg = 1 ma 2.475 2.500 2.525 v line regulation psrr 12 v v cc 25 v 2 5 mv load regulation 1 i reg 20 ma 2 5 mv temperature stability 1 tc vfb 0.1 0.2 mv/ c total output variation 1 line, load, temperature 2.450 2.500 2.550 v long-term stability 1 over 1,000 hrs at 125 c 2 12 mv oscillator initial accuracy f osc t j = 25 c 475257khz voltage stability 12 v v cc 25 v 0.2 1 % temperature stability 1 tc f t min t j t max 5% amplitude f osc v rt/ct peak-to-peak 1.6 v upper trip point v h 2.9 v lower trip point v l 1.3 v sync threshold v sync 400 600 800 mv discharge current i d 7.5 8.7 9.5 ma duty cycle limit r t = 680 w , c t = 5.3 nf, t j = 25 c465052 %
astec semiconductor current mode controller as2842/3/4/5 41 electrical characteristics (contd) electrical characteristics are guaranteed over full junction temperature range (-40 to 105 c ). ambient temperature must be derated based on power dissipation and package thermal characteristics. the conditions are: v cc = 15 v , r t = 10 k w, and c t = 3.3 nf, unless otherwise stated. to override uvlo, v cc should be raised above 17 v prior to test. parameter symbol test condition min typ max unit error amplifier input voltage v fb t j = 25 c 2.475 2.50 2.525 v input bias current i bias C 0.1 C1 m a voltage gain a vol 2 v comp 4 v 65 90 db transconductance g m 1 ma/mv unity gain bandwidth 1 gbw 0.8 1.2 mhz power supply rejection ratio psrr 12 v cc 25 v 60 70 db output sink current i compl v fb = 2.7 v, v comp = 1.1v 2 6 ma output source current i comph v fb = 2.3 v, v comp = 5 v 0.5 0.8 ma output swing high v comph v fb = 2.3 v, r l = 15 k w to ground 5 5.5 v output swing low v compl v fb = 2.7 v, r l = 15 k w to pin 8 0.7 1.1 v current sense comparator transfer gain 2,3 av cs C0.2 v sense 0.8 v 2.85 3.0 3.15 v/v i sense level shift 2 v ls v sense = 0 v 1.5 v maximum input signal 2 v comp = 5 v 0.9 1 1.1 v power supply rejection ratio psrr 12 v cc 25 v 70 db input bias current i bias C1 C10 m a propagation delay to output 1 t pd 85 150 ns output output low level v ol i sink = 20 ma 0.1 0.4 v v ol i sink = 200 ma 1.5 2.2 v output high level v oh i source = 20ma 13 13.5 v v oh i source = 200ma 12 13.5 v rise time 1 t r c l = 1 nf 50 150 ns fall time 1 t f c l = 1 nf 50 150 ns housekeeping start-up threshold v cc (on) 2842/4 15 16 17 v 2843/5 7.8 8.4 9.0 v minimum operating voltage v cc (min) 2842/4 9 10 11 v after turn on 2843/5 7.0 7.6 8.2 v output low level in uv state v ouv i sink = 20 ma, v cc = 6 v 1.5 2.0 v over-temperature shutdown 4 t ot 125 c
as2842/3/4/5 current mode controller astec semiconductor 42 notes: 1. this parameter is not 100% tested in production. 2. parameter measured at trip point of pwm latch. 3. transfer gain is the relationship between current sense input and corresponding error amplifier output at the pwm latch trip point and is mathematically expressed as follows: 4. at the over-temperature threshold, t ot , the oscillator is disabled. the 5 v reference and the pwm stages, including the pwm latch, remain powered. electrical characteristics (contd) electrical characteristics are guaranteed over full junction temperature range (-40 to 105 c ). ambient temperature must be derated based on power dissipation and package thermal characteristics. the conditions are: v cc = 15 v , r t = 10 k w, and c t = 3.3 nf, unless otherwise stated. to override uvlo, v cc should be raised above 17 v prior to test. parameter symbol test condition min typ max unit a i v v comp sense =- d d ; 0.2 v 0.8 sense pwm maximum duty cycle d max 2842/3 94 97 100 % minimum duty cycle d min 2842/3 0 % maximum duty cycle d max 2844/5 49 49.5 50 % minimum duty cycle d min 2844/5 0 % supply current start-up current i cc 2842/4, v fb = v sense = 0 v, v cc = 14 v 0.5 1.0 ma 2843/5, v fb = v sense = 0 v, v cc = 7 v 0.3 0.5 ma operating supply current i cc 917ma v cc zener voltage v z i cc = 25 ma 30 v
astec semiconductor current mode controller as2842/3/4/5 43 typical performance curves supply current vs supply voltage output voltage vs supply voltage regulator output voltage vs ambient temperature regulator short circuit current vs ambient temperature figure 2 figure 3 figure 4 figure 5 t a ?ambient temperature (?) ?0 i reg ?regulator short circuit (ma) 40 60 100 120 140 180 0 30 90 150 ?0 60 120 80 t a ?ambient temperature (?) ?0 4.90 v reg ?regulator output (v) 4.92 4.94 4.98 5.00 5.02 5.04 0 30 90 150 ?0 60 120 4.96 v cc ?supply voltage (v) 0 0 i cc ?supply current (ma) 10 15 20 25 10 15 25 5 52035 as2842/4 as2843/5 30 v cc ?supply voltage (v) 0 0 v out ?output voltage (v) 10 15 20 25 10 15 25 5 52030 as2843/5 as2842/4
as2842/3/4/5 current mode controller astec semiconductor 44 typical performance curves regulator load regulation timing capacitor vs oscillator frequency figure 6 figure 7 figure 8 figure 9 maximum duty cycle temperature stability maximum duty cycle vs timing resistor i sc ?regulator source current (ma) 0 d v reg ?regulator voltage change (mv) ?4 ?0 ?2 ? ? 0 40 60 100 140 20 80 ?6 120 150?c 25?c ?5?c r t ?timing register (k w ) 0.3 20 maximum duty cycle (%) 40 60 80 100 10 1 3 f osc ?oscillator frequency (khz) 10 0.1 c t ?timing capacitor (nf) 1 10 100 100 1 m r t = 1 k w r t = 680 w r t = 4.7 k w r t = 10 k w r t = 2.2 k w t a ?ambient temperature ?5 40 maximum duty cycle (%) 60 80 100 45 125 50 70 90 ?5 ?5 5 25 65 85 105 r t = 1 k w r t = 680 w r t = 10 k w r t = 2.2 k w
astec semiconductor current mode controller as2842/3/4/5 45 typical performance curves current sense input threshold vs error amp output voltage error amp input voltage vs ambient temperature output sink capability in under- voltage mode output saturation voltage figure 10 figure 11 figure 12 figure 13 t a ?ambient temperature (?) ?0 2.460 v fb ?error amp input voltage (v) 2.470 2.480 2.490 2.500 2.510 0 30 90 150 ?0 60 120 v fb = v comp v cc = 15 v v comp ?error amp output voltage (v) 0 0.4 v sense ?current sense input threshold (v) 0.2 0.2 0.4 0.6 1.2 1356 24 0 0.8 1.0 t a = 55?c t a = 25?c t a = 125?c v out ?output voltage (v) 0 1 i out ?output sink current (ma) 10 100 1 a 1.5 2.5 0.5 1 2 v cc = 6 v t a = 25?c i out ?output saturation current (ma) 10 0 v sat ?output saturation voltage (v) 3 ? 0 100 500 ? 2 1 sink saturation t j = 125?c t j = ?5?c t j = 25?c t j = 125?c source saturation v out ?v cc
as2842/3/4/5 current mode controller astec semiconductor 46 application information the as2842/3/4/5 family of current-mode control ics are low cost, high performance controllers which are pin compatible with the industry standard uc2842 series of devices. suitable for many switch mode power supply applications, these ics have been optimized for use in high frequency off-line and dc-dc converters. the as2842 has been enhanced to provide significantly improved performance, resulting in exceptionally better tolerances in power supply manufacturing. in addition, all electrical charac- teristics are guaranteed over the full 0 to 105 c temperature range. among the many enhance- ments are: a precision trimmed 2.5 volt refer- ence ( 0.5% of nominal at the error amplifier input), a significantly reduced propagation delay from current sense input to the ic output, a trimmed oscillator for precise duty-cycle clamp- ing, a modified flip-flop scheme that gives a true 50% duty ratio clamp on 2844/45 types, and an improved 5 v regulator for better ac noise immunity. furthermore, the as2842 provides guaranteed performance with current sense input below ground. the advanced oscillator design greatly simplifies synchronization. the device is more completely specified to guarantee all parameters that impact power supply manufacturing tolerances. section 1 theory of operation the functional block diagram of the as2842 is shown in figure 1. the ic is comprised of the six basic functions necessary to implement current mode control; the under voltage lockout; the reference; the oscillator; the error amplifier; the current sense comparator/pwm latch; and the output. the following paragraphs will describe the theory of operation of each of the functional blocks. 1.1 undervoltage lockout (uvlo) the undervoltage lockout function of the as2842 holds the ic in a low quiescent current ( 1 ma) standby mode until the supply voltage (v cc ) exceeds the upper uvlo threshold voltage. this guarantees that all of the ics internal circuitry are properly biased and fully functional before the output stage is enabled. once the ic turns on, the uvlo threshold shifts to a lower level (hys- teresis) to prevent v cc oscillations. the low quiescent current standby mode of the as2842 allows bootstrapping a technique used in off-line converters to start the ic from the rectified ac line voltage initially, after which power to the ic is provided by an auxiliary winding off the power supplys main transformer. figure 14 shows a typical bootstrap circuit where capacitor figure 14. bootstrap circuit + r < v dc min 1 ma r + c >1 ma 16 v/10 v (2842/4) 8.4 v/7.8 v (2843/5) out 6 ic enable ac line as284x 7 v cc 5 gnd aux pri sec v dc
astec semiconductor current mode controller as2842/3/4/5 47 (c) is charged via resistor (r) from the rectified ac line. when the voltage on the capacitor (v cc ) reaches the upper uvlo threshold, the ic (and hence, the power supply) turns on and the volt- age on c begins to quickly discharge due to the increased operating current. during this time, the auxiliary winding begins to supply the current necessary to run the ic. the capacitor must be sufficiently large to maintain a voltage greater than the lower uvlo threshold during start up. the value of r must be selected to provide greater than 1 ma of current at the minimum dc bus voltage (r < vdcmin/1 ma). the uvlo feature of the as2842 has significant advantages over standard 2842 devices. first, the uvlo thresholds are based on a tempera- ture compensated band gap reference rather than conventional zeners. second, the uvlo disables the output at power down, offering addi- tional protection in cases where v reg is heavily decoupled. the uvlo on some 2842 devices shuts down the 5 volt regulator only, which results in eventual power down of the output only after the 5 volt rail collapses. this can lead to unwanted stresses on the switching devices dur- ing power down. the as2842 has two separate comparators which monitor both v cc and v ref and hold the output low if either are not within specification. the as2842 family offers two different uvlo options. the as2842/4 has uvlo thresholds of 16 volts (on) and 10 volts (off). the as2843/5 has uvlo levels of 8.4 volts (on) and 7.6 volts (off). 1.2 reference (v reg and v fb ) the as2842 effectively has two precise band gap based temperature compensated voltage references. most obvious is the v reg pin (pin 8) which is the output of a series pass regulator. this 5.0 v output is normally used to provide charging current to the oscillators timing capacitor (section 1.3). in addition, there is a trimmed internal 2.5 v reference which is con- nected to the non-inverting (+) input of the error amplifier. the tolerance of the internal reference is 0.5% over the full specified temperature range, and 1% for v reg. the reference section of the as2842 is greatly improved over the standard 2842 in a number of ways. for example, in a closed loop system, the voltage at the error amplifiers inverting input (v fb , pin 1) is forced by the loop to match the voltage at the non-inverting input. thus, v fb is the voltage which sets the accuracy of the entire system. the 2.5 v reference of the as2842 is tightly trimmed for precision at v fb , including errors caused by the op amp, and is specified over temperature. this method of trim provides a precise reference voltage for the error amplifier while maintaining the original 5 v regulator speci- fications. in addition, force/sense (kelvin) bond- ing to the package pin is utilized to further im- prove the 5 v load regulation. standard 2842s, on the other hand, specify tight regulation for the 5 v output only and rate it over line, load and temperature. the voltage at v fb , which is of critical importance, is loosely specified and only at 25 c. the reference section, in addition to providing a precise dc reference voltage, also powers most of the ics internal circuitry. switching noise, therefore, can be internally coupled onto the reference. with this in mind, all of the logic within the as2842 was designed with ecl type circuitry which generates less switching noise because it runs at essentially constant current regardless of logic state. this, together with improved ac noise rejection, results in substantially less switch- ing noise on the 5 v output. the reference output is short circuit protected and can safely deliver more than 20 ma to power external circuitry.
as2842/3/4/5 current mode controller astec semiconductor 48 1.3 oscillator the newly designed oscillator of the as2842 is enhanced to give significantly improved perfor- mance. these enhancements are discussed in the following paragraphs. the basic operation of the oscillator is as follows: a simple rc network is used to program the frequency and the maximum duty ratio of the as2842 output. see figure 15. timing capacitor (c t ) is charged through timing resistor (r t ) from the fixed 5.0 v at v reg . during the charging time, the out (pin 6) is high. assuming that the output is not terminated by the pwm latch, when the voltage across c t reaches the upper oscillator trip point ( ? 3.0 v), an internal current sink from pin 4 to ground is turned on and discharges c t towards the lower trip point. during this dis- charge time, an internal clock pulse blanks the output to its low state. when the voltage across c t reaches the lower trip point ( ? 1.3 v), the current sink is turned off, the output goes high, and the cycle repeats. since the output is blanked during the discharge of c t , it is the discharge time which controls the output deadtime and hence, the maximum duty ratio. figure 15. oscillator set-up and waveforms the nature of the as2842 oscillator circuit is such that, for a given frequency, many combinations of r t and c t are possible. however, only one value of r t will yield the desired maximum duty ratio at a given frequency. since a precise maximum duty ratio clamp is critical for many power supply designs, the oscillator discharge current is trimmed in a unique manner which provides significantly improved tolerances as explained later in this section. in addition, the as2844/5 options have an internal flip-flop which effectively blanks every other output pulse (the oscillator runs at twice the output frequency), providing an absolute maximum 50% duty ratio regardless of discharge time. 1.3.1 selecting timing components r t and c t the values of r t and c t can be determined mathematically by the following expressions: 5 v reg oscillator as2842 6 output 7 v cc 8 r t c t i d 5 gnd clock pwm c t output large r t /small c t c t output small r t / large c t 4 c d r d r t t t = | ? ? ? ? = | () osc l h osc k k ln 1.63 1
astec semiconductor current mode controller as2842/3/4/5 49 table 1. r t vs maximum duty ratio r t ( w ) dmax 470 22% 560 37% 683 50% 750 54% 820 58% 910 63% 1,000 66% 1,200 72% 1,500 77% 1,800 81% 2,200 85% 2,700 88% 3,300 90% 3,900 91% 4,700 93% 5,600 94% 6,800 95% 8,200 96% 10,000 97% 18,000 98% that compensates for all of the tolerances within the device (such as the tolerances of v reg , propagation delays, the oscillator trip points, etc.) which have an effect on the frequency and maximum duty ratio. for example, if the com- bined tolerances of a particular device are 0.5% above nominal, then i d is trimmed to 0.5% above nominal. this method of trimming virtually eliminates the need to trim external oscillator components during power supply manufactur- k v l reg = - ? () v v l reg 0.736 3 k v h reg = - ? () v v h h 0.4 4 32 where f osc is the oscillator frequency, d is the maximum duty ratio, v h is the oscillators upper trip point, v l is the lower trip point, v r is the reference voltage, i d is the discharge current. table 1 lists some common values of r t and the corresponding maximum duty ratio. to select the timing components; first, use table 1 or equation (2) to determine the value of r t that will yield the desired maximum duty ratio. then, use equation (1) to calculate the value of c t. for example, for a switching frequency of 250 khz and a maxi- mum duty ratio of 50%, the value of r t , from table 1, is 683 w . applying this value to equation (1) and solving for c t gives a value of 4700 pf. in practice, some fine tuning of the initial values may be necessary during design. however, due to the advanced design of the as2842 oscillator, once the final values are determined, they will yield repeatable results, thus eliminating the need for additional trimming of the timing components during manufacturing. 1.3.2 oscillator enhancements the as2842 oscillator is trimmed to provide guaranteed duty ratio clamping. this means that the discharge current (i d ) is trimmed to a value r v i kk kk t reg d lh lh dd d d d d dd d d d d = () ( ) () ( ) () = () - () - -- -- 11 11 11 11 582 0 736 0 432 0 736 0 432 .. (. ) (. ) 2
as2842/3/4/5 current mode controller astec semiconductor 50 ing. standard 2842 devices specify or trim only for a specific value of discharge current. this makes precise and repeatable duty ratio clamp- ing virtually impossible due to other ic toler- ances. the as2844/5 provides true 50% duty ratio clamping by virtue of excluding from its flip- flop scheme, the normal output blanking associ- ated with the discharge of c t . standard as2844/ 5 devices include the output blanking associated with the discharge of c t , resulting in somewhat less than a 50% duty ratio. 1.3.3 synchronization the advanced design of the as2842 oscillator simplifies synchronizing the frequency of two or more devices to each other or to an external clock. the r t /c t doubles as a synchronization input which can easily be driven from any open collector logic output. figure 16 shows some simple circuits for implementing synchroniza- tion. 1.4 error amplifier (comp) the as2842 error amplifier is a wide bandwidth, internally compensated operational amplifier which provides a high dc open loop gain (90 db). the input to the amplifier is a pnp differential pair. the non-inverting (+) input is internally connected to the 2.5 v reference, and the invert- ing (C) input is available at pin 2 (v fb ). the output of the error amplifier consists of an active pull- down and a 0.8 ma current source pull-up as shown in figure 17. this type of output stage allows easy implementation of soft start, latched shutdown and reduced current sense clamp func- tions. it also permits wire or-ing of the error amplifier outputs of several 2842s, or complete bypass of the error amplifier when its output is forced to remain in its pull-up condition. figure 16. synchronization figure 17. error amplifier compensation + compensation network 2.50 v to pwm e/a 1 comp v fb 2 0.8 ma v out from v reg a 2842 r t /c t gnd 8 4 r t c t 5 open collector output 5 v r t /c t open collector output 3 k 2 k 2 k r t /c t 3 k cmos sync external clock
astec semiconductor current mode controller as2842/3/4/5 51 in most typical power supply designs, the converters output voltage is divided down and monitored at the error amplifiers inverting input, v fb . a simple resistor divider network is used and is scaled such that the voltage at v fb is 2.5 v when the converters output is at the desired voltage. the voltage at v fb is then compared to the internal 2.5 v reference and any slight differ- ence is amplified by the high gain of the error amplifier. the resulting error amplifier output is level shifted by two diode drops and is then divided by three to provide a 0 to 1 v reference (v e ) to one input of the current sense compara- tor. the level shifting reduces the input voltage range of the current sense input and prevents the output from going high when the error amplifier output is forced to its low state. an internal clamp limits v e to 1.0 v. the purpose of the clamp is discussed in section 1.5. 1.4.1 loop compensation loop compensation of a power supply is neces- sary to ensure stability and provide good line/load regulation and dynamic response. it is normally provided by a compensation network connected between the error amplifiers output (comp) and inverting input as shown in figure 17. the type of network used depends on the converter topology and in particular, the characteristics of the major functional blocks within the supply - i.e. the error amplifier, the modulator/switching circuit, and the output filter. in general, the network is designed such that the converters overall gain/phase response approaches that of a single pole with a C20 db/ decade rolloff, crossing unity gain at the highest possible frequency (up to f sw /4) for good dynamic response, with adequate phase margin (> 45 ) to ensure stability. figure 18 shows the gain/phase response of the error amplifier. the unity gain crossing is at 1.2 mhz with approximately 57 c of phase margin. this information is useful in determining the configuration and characteristics required for the compensation network. one of the simplest types of compensation net- works is shown in figure 19. an rc network provides a single pole which is normally set to compensate for the zero introduced by the the output capacitors esr. the frequency of the pole (f p ) is determined by the formula; |= || p 1 2 (5) p rc figure 19. a typical compensation network frequency (hz) gain (db) 10 2 210 180 150 120 90 60 30 0 ?0 ?0 240 10 1 10 3 10 4 10 5 10 6 10 7 ?0 0 20 40 60 80 phase (degrees) gain phase figure 18. gain/phase response of the as2842 + 2.50 v to pwm e/a v out r i r f c f r bias
as2842/3/4/5 current mode controller astec semiconductor 52 resistors r 1 and r f set the low frequency gain and should be chosen to provide the highest possible gain, without exceeding the unity gain crossing frequency limit of f sw /4. r bias , in con- junction with r 1 , sets the converters output volt- age; but has no effect on the loop gain/phase response. there are a few converter design considerations associated with the error amplifier. first, the values of the divider network (r 1 and r bias ) should be kept low in order to minimize errors caused by the error amplifiers input bias current ( C1.0 m a). an output voltage error equal to the product of the input bias current and the equiva- lent divider resistance, can be quite significant with divider values greater than 5 k w . low divider resistor values also help to improve the noise immunity of the sensitive v fb input. the second consideration is that the error ampli- fier will typically source only 0.8 ma; thus, the value of feedback resistance (r f ) should be no lower than 5 k w in order to maintain the error amplifiers full output range. in practice, how- ever, the feedback resistance required is usually much greater than 5 k w , hence this limitation is normally not a problem. some power supply topologies may require a more elaborate compensation network. for ex- ample, flyback and boost converters operating with continuous current have transfer functions that include a right half plane (rhp) zero. these types of systems require an additional pole element within the compensation network. a detailed discussion of loop compensation, how- ever, is beyond the scope of this application note. 1.5 i sense current comparator/pwm latch the current sense comparator (sometimes called the pwm comparator) and accompanying latch circuitry make up the pulse width modulator (pwm). it provides pulse-by-pulse current sensing/limiting and generates a variable duty ratio pulse train which controls the output voltage of the power supply. included is a high speed comparator followed by ecl type logic circuitry which has very low propagation delays and switch- ing noise. this is essential for high frequency power supply designs. the comparator has been designed to provide guaranteed performance with the current sense input below ground. the pwm latch ensures that only one pulse is al- lowed at the output for each oscillator period. the inverting input to the current sense compara- tor is internally connected to the level shifted output of the error amplifier (v e ) as discussed in the previous section. the non-inverting input is the i sense input (pin 3). it monitors the switched inductor current of the converter. figure 20 shows the current sense/pwm cir- cuitry of the as2842, and associated waveforms. the output is set high by an internal clock pulse and remains high until one of two conditions occur; 1) the oscillator times out (section 1.3 )or 2) the pwm latch is set by the current sense comparator. during the time when the output is high, the converters switching device is turned on and current flows through resistor r s . this produces a stepped ramp waveform at pin 3 as shown in figure 20. the current will continue to ramp up until it reaches the level of v e at the inverting input. at that point, the comparators output goes high, setting the pwm latch and the output pulse is then terminated. thus, v e is a variable reference for the current sense com- parator, and it controls the peak current sensed by r s on a cycle-by-cycle basis. v s varies in proportion to changes in the input voltage/cur- rent (inner control loop) while v e varies in propor- tion to changes in the converters output voltage/ current (outer control loop). the two control loops merge at the current sense comparator, produc- ing a variable duty ratio pulse train that controls the output of the converter.
astec semiconductor current mode controller as2842/3/4/5 53 figure 21. optional current transformer the current sense comparators inverting input is internally clamped to a level of 1.0 v to provide a current limit (or power limit for multiple output supplies) function. the value of r s is selected to produce 1.0 v at the maximum allowed current. for example, if 1.5 a is the maximum allowed peak inductor current, then r s is selected to equal 1 v/1.5 a = 0.66 w . in high power applica- tions, power dissipation in the current sense resistor may become intolerable. in such a case, a current transformer can be used to step down the current seen by the sense resistor. see figure 21. 1.6 output (out) the output stage of the as2842 is a high current totem-pole configuration that is well suited for directly driving power mosfets. it is capable of sourcing and sinking up to 1 a of peak current. cross conduction losses in the output stage have been minimized resulting in lower power dissipa- tion in the device. this is particularly important for high frequency operation. during undervoltage shutdown conditions, the output is active low. this eliminates the need for an external pulldown resistor. 1.7 over-temperature shutdown the as2842 has a built-in over-temperature shutdown which will limit the die temperature to 130 c typically. when the over-temperature condition is reached, the oscillator is disabled. all other circuit blocks remain operational. there- fore, when the oscillator stops running, output pulses terminate without losing control of the supply or losing any peripheral functions that may be running off the 5 v regulator. the output may go high during the final cycle, but the pwm figure 20. current sense/pwn latch circuit and waveforms v s = r s ( ) i s n r s v s n:1 i s + + ff s r 5 v reg 2r r r s comp as2842/3/4/5 error amp 2.5 v v fb 1 v 1 2 3 rt/ct 4 v s r c leadong edge filter clock pwm comparator v e v reg v cc output 8 7 6 5 gnd current sense clock output v e v s i s pri sec v in pwm logic
as2842/3/4/5 current mode controller astec semiconductor 54 latch is still fully operative, and the normal termi- nation of this cycle by the current sense com- parator will latch the output low until the over- temperature condition is rectified. cycling the power will reset the over-temperature disable mechanism, or the chip will re-start after cooling through a nominal hysteresis band. section 2 C design considerations 2.1 leading edge filter the current sensed by r s contains a leading edge spike as shown in figure 20. this spike is caused by parasitic elements within the circuit including the interwinding capacitance of the power transformer and the recovery characteris- tics of the rectifier diode(s). the spike, if not properly filtered, can cause stability problems by prematurely terminating the output pulse. a simple rc filter is used to suppress the spike. the time constant should be chosen such that it approximately equals the duration of the spike. a good choice for r 1 is 1 k w , as this value is optimum for the filter and at the same time, it simplifies the determination of r slope (section 2.2). if the duration of the spike is, for example, 100 ns, then c is determined by: c = = = time constant k ns k pf 1 (6) 100 1 100 w w 2.2 slope compensation current-mode controlled converters can experi- ence instabilities or subharmonic oscillations when operated at duty ratios greater than 50%. two different phenomena can occur as shown figure 22. slope compensation t 0 d 1 d 2 t 1 i pk v e i l 2 i l 1 i avg 2 i avg 1 m 1 m 2 (a) t 0 d 1 d 2 t 1 v e d i m 1 m 2 (b) d i' t 0 d 1 d 2 t 1 v e i l 2 i l 1 i avg 1 = i avg 2 m 1 m 2 (c) m = m 2 /2 t 0 d 1 d 2 t 1 d i m 1 m 2 (d) d i' v e m = m 2 /2
astec semiconductor current mode controller as2842/3/4/5 55 graphically in figure 22. first, current-mode controllers detect and control the peak inductor current, where as the converters output corresponds to the average inductor current. figure 22(a) clearly shows that the average inductor current (i 1 & i 2 ) changes as the duty ratio (d 1 & d 2 ) changes. note that for a fixed control voltage, the peak current is the same for any duty ratio. the difference between the peak and average currents represents an error which causes the converter to deviate from true current-mode control. second, figure 22(b) depicts how a small pertur- bation of the inductor current ( d i) can result in an unstable condition. for duty ratios less than 50 %, the disturbance will quickly converge to a steady state condition. for duty ratios greater than 50 %, d i progressively increases on each cycle, causing an unstable condition. both of these problems are corrected simulta- neously by injecting a compensating ramp into either the control voltage (v e ) as shown in figure 22(c) & (d), or to the current sense waveform at pin 3. since v e is not directly accessible, and, a positive ramp waveform is readily available from the oscillator at pin 4, it is more practical to add the slope compensation to the current waveform. this can be implemented quite simply with the addition of a single resistor, r slope , between pin 4 and pin 3 as shown in figure 23(a). r slope, in conjunction with the leading edge filter resistor, r 1 (section 2.1), forms a divider network which determines the amount of slope added to the waveform. the amount of slope added to the current waveform is inversely proportional to the value of r slope . it has been determined that the amount of slope (m) required is equal to or greater than 1/2 the downslope (m 2 ) of the induc- tor current. mathematically stated: m 3 m 2 2 (7) in some cases the required value of r slope may be low enough to affect the oscillator circuit and thus cause the frequency to shift. an emitter follower circuit can be used as a buffer for r slope as depicted in figure 23(b). slope compensation can also be used to improve noise immunity in current mode converters oper- ating at less than 50% duty ratio. power supplies figure 23. slope compensation r slope i sense r 1 i s r s r t 8 4 v reg r t /c t as2842 3 5 gnd c t r slope i sense r 1 i s r s r t 8 4 v reg r t /c t as2842 3 5 gnd c t ( a )( b ) optional buffer
as2842/3/4/5 current mode controller astec semiconductor 56 operating under very light load can experience instabilities caused by the low amplitude of the current sense ramp waveform. in such a case, any noise on the waveform can be sufficient to trip the comparator resulting in random and pre- mature pulse termination. the addition of a small amount of artificial ramp (slope compensation) can eliminate such problems without drastically affecting the overall performance of the system. 2.3 circuit layout and other considerations the electronic noise generated by any switch- mode power supply can cause severe stability problems if the circuit is not layed-out (wired) properly. a few simple layout practices will help to minimize noise problems. when building prototype breadboards, never use plug-in protoboards or wire wrap construction. for best results, do all breadboarding on double sided pcb using ground plane techniques. keep all traces and lead lengths to a minimum. avoid large loops and keep the area enclosed within any loops to a minimum. use common point grounding techniques and separate the power ground traces from the signal ground traces. locate the control ic and circuitry away from switching devices and magnetics. also, the tim- ing capacitors ground connection must be right at pin 5 as shown in figure 15. these grounding and wiring techniques are very important be- cause the resistance and inductance of the traces are significant enough to generate noise glitches which can disrupt the normal operation of the ic. also, to provide a low impedance path for high frequency noise, v cc and v ref should be decoupled to ic ground with 0.1 m f capacitors. additional decoupling in other sensitive areas may also be necessary. it is very important to locate the decoupling capacitors as close as possible to the circuit being decoupled.

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